1. Technical Field
The present disclosure relates to fabrication techniques for forming parallel plate capacitors and metal serpentine resistors together using the same sequence of processing steps. The fabrication techniques include various methods of forming inlaid metal features of disparate widths.
2. Description of the Related Art
Integrated circuits often include circuit components such as serpentine resistors and parallel plate capacitors that are made by integrating metal features with insulator structures. Electrical parameters associated with the capacitors and resistors depend on their geometry and on the material parameters of the metal and the dielectric.
Integrated circuit capacitors can be formed in a horizontal or a vertical orientation. FIG. 1A shows a perspective view of a partially formed parallel plate capacitor array 100 in a vertical orientation. Formation of the parallel plate capacitor array 100 on a semiconductor substrate 102 entails creating high aspect ratio trenches 104 in a dielectric block 106 to form very thin dielectric layers 101. The high aspect ratio trenches 104 are then filled with metal to form capacitor plates. The parallel plate capacitor array 100 can also be used as a microelectronic antifuse to protect other circuit components as described in a related U.S. patent application Ser. No. 13/931,692, entitled, “Modular Fuses and Antifuses in Integrated Circuits.”
FIG. 1B shows a top plan view of a type of resistor design, a metal serpentine resistor 110. The metal serpentine resistor 110 includes a single, continuous resistor line in a serpentine shape. It can also be thought of as an array of thin parallel wires 112, that are alternately coupled at each end. The top plan view of the metal serpentine resistor 110 shown in FIG. 1B shows an end view of the array of thin wires 112, which extend into to the page. The metal wires are incorporated into a block of non-conducting material such as the dielectric block 106. The metal serpentine resistor 110 can be made in one mask step using a serpentine-shaped mask, which is the preferred method. Alternatively, a serpentine structure can be made in two separate steps by first forming an array of parallel wires, and later connecting adjacent wires alternately at the ends. The metal serpentine resistor 110 can also be used as a microelectronic fuse to protect other circuit components, as described in the related U.S. patent application Ser. No. 13/931692, entitled, “Modular Fuses and Antifuses in Integrated Circuits.”
The metal serpentine resistor 110 and the vertically oriented parallel plate capacitor array 100 share a similar basic structure in which metal planes alternate with insulating planes. However, the metal planes in the parallel plate capacitor array 100 are shorter and wider, whereas the metal planes of the metal serpentine resistor 110 are narrower and taller. Because the two structures contain such features that vary considerably in their volume and surface areas, fabricating the metal serpentine resistor 110 and the parallel plate capacitor array 100 together would entail executing processes that are generally considered to be incompatible according to conventional methods. In other words, the two structures present disparate features to various semiconductor processing operations and therefore separate masks and process steps are carried out for each. Such disparate structures generally do not respond in the same way to a particular deposition, etching, or polishing treatment. For example, chemical-mechanical planarization (CMP) treatments tend to preferentially gouge the surface of large fields of metal, causing surface erosion and “dishing” which does not occur when smaller areas of metal are exposed. In another example, metal deposition processes tend to overfill narrow trenches while only partially filling wide trenches, causing an irregular surface height, referred to as non-uniform topography.
Generally, non-uniform topography is considered to be problematic. Non-uniform topography may occur on any of three different scales: wafer scale, die scale, and feature scale. For example, wafer-scale topography variation results from radial variation in the CMP process, from the center of a semiconductor wafer to the edge of the wafer. Wafer-scale topography variation can be addressed by adjusting CMP equipment parameters or materials used in the CMP process itself. Die-scale variation depends primarily on the pattern density of circuit features, which is largely determined by circuit mask designs. Wafer-scale and die-scale variation can be compensated for in a lithography scanner through focus-level adjustment by measuring wafer surface heights before each exposure. Today, optical or mechanical detection of long-range wafer surface height variation and focus adjustment is possible in most advanced lithography systems.
Feature-scale topography variation, however, is dependent on individual line widths, line spaces, or feature shapes, and cannot be compensated for in a lithography step because the variation is within an individual exposure field. Thus, non-uniform topography at the feature level poses a critical challenge for process developers as feature sizes continue to shrink. Reducing feature-scale non-uniformities for advanced technology generations is therefore of considerable interest to semiconductor technologists.
To avoid generating non-uniform topography, a typical solution to the problem of processing disparate features is to process them separately, i.e., first mask the narrow features while processing the wide features, and then mask the wide features while processing the narrow features. In addition, at smaller geometries, structures that could be built at the larger geometries no longer operate. For these and other reasons, such structures are generally formed in separate mask layers. However, adding masking layers to a production line is also best avoided, because each masking layer significantly increases the cost of the overall manufacturing process. For example, at smaller geometries under 45 nm, the cost of a single reticle to make a mask might be very expensive, so the ability to carry out a series of process steps with fewer reticles allows a great savings in chip production.